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[core] Document threading model rationale in ThreadModel enum
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@@ -38,25 +38,27 @@ class Framework(StrEnum):
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class ThreadModel(StrEnum):
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"""Threading model identifiers for ESPHome scheduler.
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ESPHome supports three threading models based on platform capabilities:
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ESPHome currently uses three threading models based on platform capabilities:
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SINGLE: Single-threaded platforms (ESP8266, RP2040)
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- No FreeRTOS or other RTOS
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SINGLE:
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- Single-threaded platforms (ESP8266, RP2040)
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- No RTOS task switching
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- No concurrent access to scheduler data structures
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- No atomics or locks needed
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- No atomics or locks required
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- Minimal overhead
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MULTI_NO_ATOMICS: Multi-threaded platforms without hardware atomic support (LibreTiny)
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- Uses FreeRTOS or other RTOS with multiple tasks
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- CPU lacks atomic instructions (e.g., ARM968E-S has no LDREX/STREX)
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- libatomic is not linked (would add 4-8KB flash overhead)
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- Uses explicit FreeRTOS mutex locking for synchronization
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MULTI_NO_ATOMICS:
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- Multi-threaded platforms without hardware atomic RMW support (e.g. LibreTiny BK7231N)
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- Uses FreeRTOS or another RTOS with multiple tasks
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- CPU lacks exclusive load/store instructions (ARM968E-S has no LDREX/STREX)
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- std::atomic cannot provide lock-free RMW; libatomic is avoided to save flash (4–8 KB)
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- Scheduler uses explicit FreeRTOS mutexes for synchronization
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MULTI_ATOMICS: Multi-threaded platforms with hardware atomic support (ESP32, Host)
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- Uses FreeRTOS or other RTOS with multiple tasks
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- CPU has native atomic instructions (e.g., ESP32 has S32C1I, ARM Cortex has LDREX/STREX)
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- Uses std::atomic for lock-free synchronization
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- Better performance through reduced lock contention
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MULTI_ATOMICS:
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- Multi-threaded platforms with hardware atomic RMW support (ESP32, Cortex-M, Host)
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- CPU provides native atomic instructions (ESP32 S32C1I, ARM LDREX/STREX)
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- std::atomic is used for lock-free synchronization
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- Reduced contention and better performance
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"""
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SINGLE = "ESPHOME_THREAD_SINGLE"
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