mirror of
https://github.com/ARM-software/workload-automation.git
synced 2024-10-07 11:21:30 +01:00
295 lines
7.7 KiB
C
Executable File
295 lines
7.7 KiB
C
Executable File
/* Copyright 2013-2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* pmu_logger.c - Kernel module to log the CCI PMU counters
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/debugfs.h>
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#include <linux/timer.h>
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#include <asm/io.h>
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#define MODULE_NAME "cci_pmu_logger"
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// CCI_BASE needs to be modified to point to the mapped location of CCI in
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// memory on your device.
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#define CCI_BASE 0x2C090000 // TC2
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//#define CCI_BASE 0x10D20000
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#define CCI_SIZE 0x00010000
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#define PMCR 0x100
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#define PMCR_CEN (1 << 0)
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#define PMCR_RST (1 << 1)
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#define PMCR_CCR (1 << 2)
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#define PMCR_CCD (1 << 3)
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#define PMCR_EX (1 << 4)
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#define PMCR_DP (1 << 5)
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#define CC_BASE 0x9000
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#define PC0_BASE 0xA000
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#define PC1_BASE 0xB000
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#define PC2_BASE 0xC000
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#define PC3_BASE 0xD000
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#define PC_ESR 0x0
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#define CNT_VALUE 0x4
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#define CNT_CONTROL 0x8
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#define CNT_ENABLE (1 << 0)
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u32 counter0_event = 0x6A;
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u32 counter1_event = 0x63;
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u32 counter2_event = 0x8A;
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u32 counter3_event = 0x83;
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u32 enable_console = 0;
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u32 enable_ftrace = 1;
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void *cci_base = 0;
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static struct dentry *module_debugfs_root;
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static int enabled = false;
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u32 delay = 10; //jiffies. This translates to 1 sample every 100 ms
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struct timer_list timer;
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static void call_after_delay(void)
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{
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timer.expires = jiffies + delay;
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add_timer(&timer);
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}
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static void setup_and_call_after_delay(void (*fn)(unsigned long))
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{
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init_timer(&timer);
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timer.data = (unsigned long)&timer;
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timer.function = fn;
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call_after_delay();
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}
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static void print_counter_configuration(void)
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{
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if (enable_ftrace)
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trace_printk("Counter_0: %02x Counter_1: %02x Counter_2: %02x Counter_3: %02x\n", \
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counter0_event, counter1_event, counter2_event, counter3_event);
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if (enable_console)
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printk("Counter_0: %02x Counter_1: %02x Counter_2: %02x Counter_3: %02x\n", \
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counter0_event, counter1_event, counter2_event, counter3_event);
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}
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static void initialize_cci_pmu(void)
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{
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u32 val;
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// Select the events counted
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iowrite32(counter0_event, cci_base + PC0_BASE + PC_ESR);
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iowrite32(counter1_event, cci_base + PC1_BASE + PC_ESR);
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iowrite32(counter2_event, cci_base + PC2_BASE + PC_ESR);
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iowrite32(counter3_event, cci_base + PC3_BASE + PC_ESR);
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// Enable the individual PMU counters
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iowrite32(CNT_ENABLE, cci_base + PC0_BASE + CNT_CONTROL);
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iowrite32(CNT_ENABLE, cci_base + PC1_BASE + CNT_CONTROL);
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iowrite32(CNT_ENABLE, cci_base + PC2_BASE + CNT_CONTROL);
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iowrite32(CNT_ENABLE, cci_base + PC3_BASE + CNT_CONTROL);
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iowrite32(CNT_ENABLE, cci_base + CC_BASE + CNT_CONTROL);
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// Reset the counters and configure the Cycle Count Divider
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val = ioread32(cci_base + PMCR);
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iowrite32(val | PMCR_RST | PMCR_CCR | PMCR_CCD, cci_base + PMCR);
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}
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static void enable_cci_pmu_counters(void)
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{
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u32 val = ioread32(cci_base + PMCR);
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iowrite32(val | PMCR_CEN, cci_base + PMCR);
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}
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static void disable_cci_pmu_counters(void)
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{
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u32 val = ioread32(cci_base + PMCR);
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iowrite32(val & ~PMCR_CEN, cci_base + PMCR);
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}
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static void trace_values(unsigned long arg)
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{
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u32 cycles;
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u32 counter[4];
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cycles = ioread32(cci_base + CC_BASE + CNT_VALUE);
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counter[0] = ioread32(cci_base + PC0_BASE + CNT_VALUE);
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counter[1] = ioread32(cci_base + PC1_BASE + CNT_VALUE);
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counter[2] = ioread32(cci_base + PC2_BASE + CNT_VALUE);
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counter[3] = ioread32(cci_base + PC3_BASE + CNT_VALUE);
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if (enable_ftrace)
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trace_printk("Cycles: %08x Counter_0: %08x"
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" Counter_1: %08x Counter_2: %08x Counter_3: %08x\n", \
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cycles, counter[0], counter[1], counter[2], counter[3]);
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if (enable_console)
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printk("Cycles: %08x Counter_0: %08x"
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" Counter_1: %08x Counter_2: %08x Counter_3: %08x\n", \
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cycles, counter[0], counter[1], counter[2], counter[3]);
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if (enabled) {
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u32 val;
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// Reset the counters
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val = ioread32(cci_base + PMCR);
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iowrite32(val | PMCR_RST | PMCR_CCR, cci_base + PMCR);
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call_after_delay();
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}
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}
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static ssize_t read_control(struct file *file, char __user *buf, size_t count, loff_t *ppos)
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{
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char status[16];
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/* printk(KERN_DEBUG "%s\n", __func__); */
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if (enabled)
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snprintf(status, 16, "enabled\n");
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else
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snprintf(status, 16, "disabled\n");
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return simple_read_from_buffer(buf, count, ppos, status, strlen(status));
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}
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static ssize_t write_control(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
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{
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if (enabled) {
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disable_cci_pmu_counters();
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enabled = false;
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} else {
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initialize_cci_pmu();
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enable_cci_pmu_counters();
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enabled = true;
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print_counter_configuration();
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setup_and_call_after_delay(trace_values);
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}
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return count;
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}
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static ssize_t read_values(struct file *file, char __user *buf, size_t count, loff_t *ppos)
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{
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char values[256];
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/* u32 val; */
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snprintf(values, 256, "Cycles: %08x Counter_0: %08x"
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" Counter_1: %08x Counter_2: %08x Counter_3: %08x\n", \
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ioread32(cci_base + CC_BASE + CNT_VALUE), \
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ioread32(cci_base + PC0_BASE + CNT_VALUE), \
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ioread32(cci_base + PC1_BASE + CNT_VALUE), \
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ioread32(cci_base + PC2_BASE + CNT_VALUE), \
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ioread32(cci_base + PC3_BASE + CNT_VALUE));
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return simple_read_from_buffer(buf, count, ppos, values, strlen(values));
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}
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static const struct file_operations control_fops = {
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.owner = THIS_MODULE,
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.read = read_control,
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.write = write_control,
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};
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static const struct file_operations value_fops = {
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.owner = THIS_MODULE,
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.read = read_values,
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};
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static int __init pmu_logger_init(void)
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{
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struct dentry *retval;
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module_debugfs_root = debugfs_create_dir(MODULE_NAME, NULL);
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if (!module_debugfs_root || IS_ERR(module_debugfs_root)) {
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printk(KERN_ERR "error creating debugfs dir.\n");
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goto out;
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}
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retval = debugfs_create_file("control", S_IRUGO | S_IWUGO, module_debugfs_root, NULL, &control_fops);
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if (!retval)
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goto out;
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retval = debugfs_create_file("values", S_IRUGO, module_debugfs_root, NULL, &value_fops);
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if (!retval)
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goto out;
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retval = debugfs_create_bool("enable_console", S_IRUGO | S_IWUGO, module_debugfs_root, &enable_console);
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if (!retval)
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goto out;
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retval = debugfs_create_bool("enable_ftrace", S_IRUGO | S_IWUGO, module_debugfs_root, &enable_ftrace);
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if (!retval)
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goto out;
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retval = debugfs_create_u32("period_jiffies", S_IRUGO | S_IWUGO, module_debugfs_root, &delay);
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if (!retval)
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goto out;
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retval = debugfs_create_x32("counter0", S_IRUGO | S_IWUGO, module_debugfs_root, &counter0_event);
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if (!retval)
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goto out;
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retval = debugfs_create_x32("counter1", S_IRUGO | S_IWUGO, module_debugfs_root, &counter1_event);
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if (!retval)
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goto out;
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retval = debugfs_create_x32("counter2", S_IRUGO | S_IWUGO, module_debugfs_root, &counter2_event);
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if (!retval)
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goto out;
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retval = debugfs_create_x32("counter3", S_IRUGO | S_IWUGO, module_debugfs_root, &counter3_event);
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if (!retval)
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goto out;
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cci_base = ioremap(CCI_BASE, CCI_SIZE);
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if (!cci_base)
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goto out;
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printk(KERN_INFO "CCI PMU Logger loaded.\n");
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return 0;
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out:
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debugfs_remove_recursive(module_debugfs_root);
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return 1;
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}
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static void __exit pmu_logger_exit(void)
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{
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if (module_debugfs_root) {
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debugfs_remove_recursive(module_debugfs_root);
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module_debugfs_root = NULL;
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}
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if (cci_base)
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iounmap(cci_base);
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printk(KERN_INFO "CCI PMU Logger removed.\n");
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}
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module_init(pmu_logger_init);
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module_exit(pmu_logger_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Punit Agrawal");
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MODULE_DESCRIPTION("logger for CCI PMU counters");
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