mirror of
https://github.com/ARM-software/workload-automation.git
synced 2024-10-07 19:31:18 +01:00
97 lines
5.1 KiB
Plaintext
97 lines
5.1 KiB
Plaintext
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BOARD: HBI0249
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TITLE: V2P-CA15_A7 Configuration File
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[DCCS]
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TOTALDCCS: 1 ;Total Number of DCCS
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M0FILE: dbb_v110.ebf ;DCC0 Filename
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M0MODE: MICRO ;DCC0 Programming Mode
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[FPGAS]
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TOTALFPGAS: 0 ;Total Number of FPGAs
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[TAPS]
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TOTALTAPS: 3 ;Total Number of TAPs
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T0NAME: STM32TMC ;TAP0 Device Name
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T0FILE: NONE ;TAP0 Filename
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T0MODE: NONE ;TAP0 Programming Mode
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T1NAME: STM32CM3 ;TAP1 Device Name
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T1FILE: NONE ;TAP1 Filename
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T1MODE: NONE ;TAP1 Programming Mode
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T2NAME: CORTEXA15 ;TAP2 Device Name
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T2FILE: NONE ;TAP2 Filename
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T2MODE: NONE ;TAP2 Programming Mode
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[OSCCLKS]
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TOTALOSCCLKS: 9 ;Total Number of OSCCLKS
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OSC0: 50.0 ;CPUREFCLK0 A15 CPU (20:1 - 1.0GHz)
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OSC1: 50.0 ;CPUREFCLK1 A15 CPU (20:1 - 1.0GHz)
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OSC2: 40.0 ;CPUREFCLK0 A7 CPU (20:1 - 800MHz)
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OSC3: 40.0 ;CPUREFCLK1 A7 CPU (20:1 - 800MHz)
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OSC4: 40.0 ;HSBM AXI (40MHz)
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OSC5: 23.75 ;HDLCD (23.75MHz - TC PLL is in bypass)
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OSC6: 50.0 ;SMB (50MHz)
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OSC7: 50.0 ;SYSREFCLK (20:1 - 1.0GHz, ACLK - 500MHz)
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OSC8: 50.0 ;DDR2 (8:1 - 400MHz)
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[SCC REGISTERS]
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TOTALSCCS: 33 ;Total Number of SCC registers
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;SCC: 0x010 0x000003D0 ;Remap to NOR0
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SCC: 0x010 $SCC_0x010 ;Switch between NOR0/NOR1
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SCC: 0x01C 0xFF00FF00 ;CFGRW3 - SMC CS6/7 N/U
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SCC: 0x118 0x01CD1011 ;CFGRW17 - HDLCD PLL external bypass
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;SCC: 0x700 0x00320003 ;CFGRW48 - [25:24]Boot CPU [28]Boot Cluster (default CA7_0)
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SCC: 0x700 $SCC_0x700 ;CFGRW48 - [25:24]Boot CPU [28]Boot Cluster (default CA7_0)
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; Bootmon configuration:
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; [15]: A7 Event stream generation (default: disabled)
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; [14]: A15 Event stream generation (default: disabled)
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; [13]: Power down the non-boot cluster (default: disabled)
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; [12]: Use per-cpu mailboxes for power management (default: disabled)
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; [11]: A15 executes WFEs as nops (default: disabled)
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SCC: 0x400 0x33330c00 ;CFGREG41 - A15 configuration register 0 (Default 0x33330c80)
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; [29:28] SPNIDEN
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; [25:24] SPIDEN
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; [21:20] NIDEN
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; [17:16] DBGEN
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; [13:12] CFGTE
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; [9:8] VINITHI_CORE
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; [7] IMINLN
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; [3:0] CLUSTER_ID
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;Set the CPU clock PLLs
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SCC: 0x120 0x022F1010 ;CFGRW19 - CA15_0 PLL control - 20:1 (lock OFF)
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SCC: 0x124 0x0011710D ;CFGRW20 - CA15_0 PLL value
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SCC: 0x128 0x022F1010 ;CFGRW21 - CA15_1 PLL control - 20:1 (lock OFF)
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SCC: 0x12C 0x0011710D ;CFGRW22 - CA15_1 PLL value
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SCC: 0x130 0x022F1010 ;CFGRW23 - CA7_0 PLL control - 20:1 (lock OFF)
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SCC: 0x134 0x0011710D ;CFGRW24 - CA7_0 PLL value
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SCC: 0x138 0x022F1010 ;CFGRW25 - CA7_1 PLL control - 20:1 (lock OFF)
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SCC: 0x13C 0x0011710D ;CFGRW26 - CA7_1 PLL value
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;Power management interface
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SCC: 0xC00 0x00000005 ;Control: [0]PMI_EN [1]DBG_EN [2]SPC_SYSCFG
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SCC: 0xC04 0x060E0356 ;Latency in uS max: [15:0]DVFS [31:16]PWRUP
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SCC: 0xC08 0x00000000 ;Reserved
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SCC: 0xC0C 0x00000000 ;Reserved
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;CA15 performance values: 0xVVVFFFFF
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SCC: 0xC10 0x384061A8 ;CA15 PERFVAL0, 900mV, 20,000*20= 500MHz
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SCC: 0xC14 0x38407530 ;CA15 PERFVAL1, 900mV, 25,000*20= 600MHz
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SCC: 0xC18 0x384088B8 ;CA15 PERFVAL2, 900mV, 30,000*20= 700MHz
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SCC: 0xC1C 0x38409C40 ;CA15 PERFVAL3, 900mV, 35,000*20= 800MHz
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SCC: 0xC20 0x3840AFC8 ;CA15 PERFVAL4, 900mV, 40,000*20= 900MHz
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SCC: 0xC24 0x3840C350 ;CA15 PERFVAL5, 900mV, 45,000*20=1000MHz
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SCC: 0xC28 0x3CF0D6D8 ;CA15 PERFVAL6, 975mV, 50,000*20=1100MHz
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SCC: 0xC2C 0x41A0EA60 ;CA15 PERFVAL7, 1050mV, 55,000*20=1200MHz
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;CA7 performance values: 0xVVVFFFFF
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SCC: 0xC30 0x3840445C ;CA7 PERFVAL0, 900mV, 10,000*20= 350MHz
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SCC: 0xC34 0x38404E20 ;CA7 PERFVAL1, 900mV, 15,000*20= 400MHz
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SCC: 0xC38 0x384061A8 ;CA7 PERFVAL2, 900mV, 20,000*20= 500MHz
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SCC: 0xC3C 0x38407530 ;CA7 PERFVAL3, 900mV, 25,000*20= 600MHz
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SCC: 0xC40 0x384088B8 ;CA7 PERFVAL4, 900mV, 30,000*20= 700MHz
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SCC: 0xC44 0x38409C40 ;CA7 PERFVAL5, 900mV, 35,000*20= 800MHz
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SCC: 0xC48 0x3CF0AFC8 ;CA7 PERFVAL6, 975mV, 40,000*20= 900MHz
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SCC: 0xC4C 0x41A0C350 ;CA7 PERFVAL7, 1050mV, 45,000*20=1000MHz
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