[ci] Merge components with different buses to reduce CI time (#11251)

Co-authored-by: Jesse Hills <3060199+jesserockz@users.noreply.github.com>

tests/components/wk2132_spi/common.yaml

@@ -1,20 +1,20 @@
 wk2132_spi:
-  - id: wk2132_spi_id
+  - id: wk2132_spi_bridge
     cs_pin: ${cs_pin}
     crystal: 11059200
     data_rate: 1MHz
     uart:
-      - id: wk2132_spi_id0
+      - id: wk2132_spi_uart0
         channel: 0
         baud_rate: 115200
         stop_bits: 1
         parity: none
-      - id: wk2132_spi_id1
+      - id: wk2132_spi_uart1
         channel: 1
         baud_rate: 9600
 
 # Ensures a sensor doesn't break validation
 sensor:
   - platform: a02yyuw
-    uart_id: wk2132_spi_id1
+    uart_id: wk2132_spi_uart1
     id: distance_sensor

tests/components/wk2132_spi/test.esp32-idf.yaml

@@ -3,5 +3,6 @@ substitutions:
 
 packages:
   spi: !include ../../test_build_components/common/spi/esp32-idf.yaml
+  uart_bridge_2: !include ../../test_build_components/common/uart_bridge_2/esp32-idf.yaml
 
 <<: !include common.yaml

tests/components/wk2132_spi/test.esp32-s3-idf.yaml

@@ -6,5 +6,6 @@ substitutions:
 
 packages:
   spi: !include ../../test_build_components/common/spi/esp32-s3-idf.yaml
+  uart_bridge_2: !include ../../test_build_components/common/uart_bridge_2/esp32-s3-idf.yaml
 
 <<: !include common.yaml