[ci] Merge components with different buses to reduce CI time (#11251)

Co-authored-by: Jesse Hills <3060199+jesserockz@users.noreply.github.com>
2025-10-30 14:43:51 +00:00 · 2025-10-15 17:36:03 -10:00
parent f2e0a412db
commit 14d76e9e4e
78 changed files with 954 additions and 266 deletions
--- a/tests/components/ssd1306_spi/common.yaml
+++ b/tests/components/ssd1306_spi/common.yaml
@@ -1,5 +1,6 @@
 display:
  - platform: ssd1306_spi
+    id: ssd1306_spi_display
    model: SSD1306 128x64
    cs_pin: ${cs_pin}
    dc_pin: ${dc_pin}