1
0
mirror of https://github.com/esphome/esphome.git synced 2025-09-17 18:52:19 +01:00

Extend 'uart:' with 'invert:' for esp32 (#1586)

This commit is contained in:
needspeed
2021-03-06 14:25:07 +01:00
committed by GitHub
parent e62bf333a2
commit 0f151a8f6b
4 changed files with 13 additions and 2 deletions

View File

@@ -2,7 +2,7 @@ import esphome.codegen as cg
import esphome.config_validation as cv
from esphome import pins, automation
from esphome.const import CONF_BAUD_RATE, CONF_ID, CONF_RX_PIN, CONF_TX_PIN, CONF_UART_ID, \
CONF_DATA, CONF_RX_BUFFER_SIZE
CONF_DATA, CONF_RX_BUFFER_SIZE, CONF_INVERT
from esphome.core import CORE, coroutine
CODEOWNERS = ['@esphome/core']
@@ -47,6 +47,8 @@ CONFIG_SCHEMA = cv.All(cv.Schema({
cv.Optional(CONF_TX_PIN): pins.output_pin,
cv.Optional(CONF_RX_PIN): validate_rx_pin,
cv.Optional(CONF_RX_BUFFER_SIZE, default=256): cv.validate_bytes,
cv.SplitDefault(CONF_INVERT, esp32=False): cv.All(cv.only_on_esp32,
cv.boolean),
cv.Optional(CONF_STOP_BITS, default=1): cv.one_of(1, 2, int=True),
cv.Optional(CONF_DATA_BITS, default=8): cv.int_range(min=5, max=8),
cv.Optional(CONF_PARITY, default="NONE"): cv.enum(UART_PARITY_OPTIONS, upper=True)
@@ -65,6 +67,8 @@ def to_code(config):
if CONF_RX_PIN in config:
cg.add(var.set_rx_pin(config[CONF_RX_PIN]))
cg.add(var.set_rx_buffer_size(config[CONF_RX_BUFFER_SIZE]))
if CONF_INVERT in config:
cg.add(var.set_invert(config[CONF_INVERT]))
cg.add(var.set_stop_bits(config[CONF_STOP_BITS]))
cg.add(var.set_data_bits(config[CONF_DATA_BITS]))
cg.add(var.set_parity(config[CONF_PARITY]))