sascha/esphome
1
0
Fork 0
mirror of https://github.com/esphome/esphome.git synced 2025-09-22 05:02:23 +01:00
Code Issues Releases Wiki Activity

Displays

Browse Source
This commit is contained in:
Otto Winter
2018-08-18 21:40:59 +02:00
parent 5170a7cdf4
commit 03249780fd
18 changed files with 823 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
esphomeyaml/components/spi.py
View File

@@ -2,18 +2,18 @@ import voluptuous as vol
import esphomeyaml.config_validation as cv
from esphomeyaml import pins
from esphomeyaml.const import CONF_CLK, CONF_ID, CONF_MISO, CONF_MOSI
from esphomeyaml.const import CONF_CLK_PIN, CONF_ID, CONF_MISO_PIN, CONF_MOSI_PIN
from esphomeyaml.helpers import App, Pvariable, esphomelib_ns, gpio_input_pin_expression, \
gpio_output_pin_expression
gpio_output_pin_expression, add
SPIComponent = esphomelib_ns.SPIComponent
SPI_SCHEMA = vol.Schema({
SPI_SCHEMA = vol.All(vol.Schema({
cv.GenerateID(): cv.declare_variable_id(SPIComponent),
vol.Required(CONF_CLK): pins.gpio_output_pin_schema,
vol.Required(CONF_MISO): pins.gpio_input_pin_schema,
vol.Optional(CONF_MOSI): pins.gpio_output_pin_schema,
})
vol.Required(CONF_CLK_PIN): pins.gpio_output_pin_schema,
vol.Optional(CONF_MISO_PIN): pins.gpio_input_pin_schema,
vol.Optional(CONF_MOSI_PIN): pins.gpio_output_pin_schema,
}), cv.has_at_least_one_key(CONF_MISO_PIN, CONF_MOSI_PIN))
CONFIG_SCHEMA = vol.All(cv.ensure_list, [SPI_SCHEMA])
@@ -21,17 +21,18 @@ CONFIG_SCHEMA = vol.All(cv.ensure_list, [SPI_SCHEMA])
def to_code(config):
for conf in config:
clk = None
for clk in gpio_output_pin_expression(conf[CONF_CLK]):
for clk in gpio_output_pin_expression(conf[CONF_CLK_PIN]):
yield
miso = None
for miso in gpio_input_pin_expression(conf[CONF_MISO]):
yield
mosi = None
if CONF_MOSI in conf:
for mosi in gpio_output_pin_expression(conf[CONF_MOSI]):
rhs = App.init_spi(clk)
spi = Pvariable(conf[CONF_ID], rhs)
if CONF_MISO_PIN in conf:
for miso in gpio_input_pin_expression(conf[CONF_MISO_PIN]):
yield
rhs = App.init_spi(clk, miso, mosi)
Pvariable(conf[CONF_ID], rhs)
add(spi.set_miso(miso))
if CONF_MOSI_PIN in conf:
for mosi in gpio_input_pin_expression(conf[CONF_MOSI_PIN]):
yield
add(spi.set_mosi(mosi))
BUILD_FLAGS = '-DUSE_SPI'