From f9a99443c4623f8508db71edbf5446bb82f62da9 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Sat, 1 Nov 2025 03:02:40 +0000 Subject: [PATCH] build(deps): bump assets/syntaxes/02_Extra/SystemVerilog Bumps [assets/syntaxes/02_Extra/SystemVerilog](https://github.com/TheClams/SystemVerilog) from `7eca705` to `b340f1c`. - [Commits](https://github.com/TheClams/SystemVerilog/compare/7eca705e87f87b94478fe222fc91d54d488cc8e3...b340f1c7f6a38d4da9f77be5abd6d455e5da7641) --- updated-dependencies: - dependency-name: assets/syntaxes/02_Extra/SystemVerilog dependency-version: b340f1c7f6a38d4da9f77be5abd6d455e5da7641 dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- assets/syntaxes/02_Extra/SystemVerilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/assets/syntaxes/02_Extra/SystemVerilog b/assets/syntaxes/02_Extra/SystemVerilog index 7eca705e..b340f1c7 160000 --- a/assets/syntaxes/02_Extra/SystemVerilog +++ b/assets/syntaxes/02_Extra/SystemVerilog @@ -1 +1 @@ -Subproject commit 7eca705e87f87b94478fe222fc91d54d488cc8e3 +Subproject commit b340f1c7f6a38d4da9f77be5abd6d455e5da7641