diff --git a/assets/syntaxes/02_Extra/SystemVerilog b/assets/syntaxes/02_Extra/SystemVerilog
index 7eca705e..b340f1c7 160000
--- a/assets/syntaxes/02_Extra/SystemVerilog
+++ b/assets/syntaxes/02_Extra/SystemVerilog
@@ -1 +1 @@
-Subproject commit 7eca705e87f87b94478fe222fc91d54d488cc8e3
+Subproject commit b340f1c7f6a38d4da9f77be5abd6d455e5da7641