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Add Verilog syntax test file
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Mohamed Abdelnour
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David Peter
David Peter
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63043d4a60
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172
tests/syntax-tests/source/Verilog/div_pipelined.v
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172
tests/syntax-tests/source/Verilog/div_pipelined.v
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// Copyright 2018 Schuyler Eldridge
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// Implements a fixed-point parameterized pipelined division
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// operation. Outputs are expected to be on range [-1,1), techincally
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// [-1,2^(BITS-1)-1/2^(BITS-1)]. There is no convergent rounding.
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//
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// [TODO] Implement optional convergent rounding and some form of
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// variable output binary point placement. There are arguments in
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// these changes that make sense (specifically, adding an additional
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// bit results in a gain of one value when all the other 2^6 values
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// greater than 1 aren't used). Other improvements that are needed: 1)
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// quotient_gen is getting smaller by one bit in every stage, it would
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// make more sense to generate this as such, 2) there's some weird
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// initial behavior after rst_n is deasserted, you get weird output on
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// the quotient line for a number of cycles.
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//
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// [TODO] This doesn't exactly behave as expected if you specify
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// different BITS and STAGES parameters (which for a functional
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// module, should be implemented). Note, that this technically works,
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// but needs more investigation to fully understand its properties.
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`timescale 1ns / 1ps
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module div_pipelined
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(
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input clk,
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input rst_n,
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input start,
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input [BITS-1:0] dividend,
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input [BITS-1:0] divisor,
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output reg data_valid,
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output reg div_by_zero,
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output reg [STAGES-1:0] quotient
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// output reg [7:0] quotient_correct
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);
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// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
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// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
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// OVERWRITTEN!
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parameter
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BITS = 8,
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STAGES = BITS;
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// y = a/bQ
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reg [STAGES-1:0] start_gen, negative_quotient_gen, div_by_zero_gen;
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reg [BITS*2*(STAGES-1)-1:0] dividend_gen, divisor_gen, quotient_gen;
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wire [BITS-1:0] pad_dividend;
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wire [BITS-2:0] pad_divisor;
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assign pad_dividend = 0;
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assign pad_divisor = 0;
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// sign conversion stage
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always @ (posedge clk or negedge rst_n)
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begin
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if (!rst_n) begin
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div_by_zero_gen[0] <= 0;
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start_gen[0] <=0;
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negative_quotient_gen[0] <= 0;
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dividend_gen[BITS*2-1:0] <= 0;
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divisor_gen[BITS*2-1:0] <= 0; end
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else begin
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div_by_zero_gen[0] <= (divisor == 0);
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start_gen[0] <= start;
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negative_quotient_gen[0] <= dividend[BITS-1] ^ divisor[BITS-1];
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dividend_gen[BITS*2-1:0] <= (dividend[BITS-1]) ? ~{dividend,pad_dividend} + 1 : {dividend,pad_dividend};
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divisor_gen[BITS*2-1:0] <= (divisor [BITS-1]) ? ~{1'b1,divisor, pad_divisor} + 1 : {1'b0,divisor, pad_divisor};
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end
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end
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// first computation stage
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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div_by_zero_gen[1] <= 0;
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start_gen[1] <= 0;
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negative_quotient_gen[1] <= 0;
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divisor_gen[BITS*2*2-1:BITS*2] <= 0;
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quotient_gen[BITS*2-1:0] <= 0;
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dividend_gen[BITS*2*2-1:BITS*2] <= 0;
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end
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else begin
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div_by_zero_gen[1] <= div_by_zero_gen[0];
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start_gen[1] <= start_gen[0];
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negative_quotient_gen[1] <= negative_quotient_gen[0];
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divisor_gen[BITS*2*2-1:BITS*2] <= divisor_gen[BITS*2-1:0] >> 1;
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if ( dividend_gen[BITS*2-1:0] >= divisor_gen[BITS*2-1:0]) begin
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quotient_gen[BITS*2-1:0] <= 1 << STAGES - 2;
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dividend_gen[BITS*2*2-1:BITS*2] <= dividend_gen[BITS*2-1:0] - divisor_gen[BITS*2-1:0];
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end
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else begin
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quotient_gen[BITS*2-1:0] <= 0;
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dividend_gen[BITS*2*2-1:BITS*2] <= dividend_gen[BITS*2-1:0];
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end
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end // else: !if(!rst_n)
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end // always @ (posedge clk)
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generate
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genvar i;
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for (i = 1; i < STAGES - 2; i = i + 1) begin : pipeline
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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div_by_zero_gen[i+1] <= 0;
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start_gen[i+1] <= 0;
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negative_quotient_gen[i+1] <= 0;
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divisor_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= 0;
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quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= 0;
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dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= 0;
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end
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else begin
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div_by_zero_gen[i+1] <= div_by_zero_gen[i];
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start_gen[i+1] <= start_gen[i];
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negative_quotient_gen[i+1] <= negative_quotient_gen[i];
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divisor_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= divisor_gen[BITS*2*(i+1)-1:BITS*2*i] >> 1;
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if (dividend_gen[BITS*2*(i+1)-1:BITS*2*i] >= divisor_gen[BITS*2*(i+1)-1:BITS*2*i]) begin
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quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= quotient_gen[BITS*2*i-1:BITS*2*(i-1)] | (1 << (STAGES-2-i));
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dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= dividend_gen[BITS*2*(i+1)-1:BITS*2*i] - divisor_gen[BITS*2*(i+1)-1:BITS*2*i];
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end
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else begin
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quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= quotient_gen[BITS*2*i-1:BITS*2*(i-1)];
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dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= dividend_gen[BITS*2*(i+1)-1:BITS*2*i];
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end
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end // else: !if(!rst_n)
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end // always @ (posedge clk or negedge rst_n)
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end // block: pipeline
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endgenerate
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// last computation stage
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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div_by_zero_gen[STAGES-1] <= 0;
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start_gen[STAGES-1] <= 0;
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negative_quotient_gen[STAGES-1] <= 0;
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quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= 0;
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end
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else begin
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div_by_zero_gen[STAGES-1] <= div_by_zero_gen[STAGES-2];
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start_gen[STAGES-1] <= start_gen[STAGES-2];
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negative_quotient_gen[STAGES-1] <= negative_quotient_gen[STAGES-2];
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if ( dividend_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] >= divisor_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] )
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quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= quotient_gen[BITS*2*(STAGES-2)-1:BITS*2*(STAGES-3)] | 1;
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else
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quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= quotient_gen[BITS*2*(STAGES-2)-1:BITS*2*(STAGES-3)];
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end // else: !if(!rst_n)
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end // always @ (posedge clk)
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// sign conversion stage
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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div_by_zero <= 0;
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data_valid <= 0;
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quotient <= 0;
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end
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else begin
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div_by_zero <= div_by_zero_gen[STAGES-1];
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data_valid <= start_gen[STAGES-1];
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quotient <= (negative_quotient_gen[STAGES-1]) ? ~quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] + 1 : quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)];
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end
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end
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endmodule
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